Currently, the wafer level chip size packaging (WLCSP) technology is the mainstream semiconductor chip packaging technology, in which a full wafer is packaged and tested, and then is cut to acquire individual finished chips. By using this packaging technology, the packaged individual finished chip almost has the same size as an individual crystalline grain, which meets the market requirement for lighter, smaller, shorter, thinner and cheaper microelectronic products. The wafer level chip size packaging technology is a hotspot in the current packaging field, and represents a development trend in the future.
Reference is made to FIG. 1, which shows a wafer level image sensing chip package. A wafer 1 is aligned and laminated with a protective substrate 2. Support units 3 are between the wafer 1 and the protective substrate 2 to form a gap between the wafer 1 and the protective substrate 2, so as to prevent the protective substrate 2 from directly contacting with the wafer 1. The wafer 1 includes multiple image sensing chips 10 arranged in a grid. Each image sensing chip 10 includes an image sensing region 11 and contact pads 12. The multiple support units 3 are arranged in a grid on the protective substrate 2, and correspond to the image sensing chips 10. After the protective substrate 2 is aligned and laminated with the wafer 1, the support units 3 enclose the image sensing region 11. The wafer 1 has a first surface and a second surface opposite the first surface. The image sensing region 11 and the contact pads 12 are arranged on the side of the first surface of the wafer.
In order to realize electrical connection between the contact pad 12 and other circuits, an opening 22 extending towards the first surface is provided on the side of the second surface of the wafer 1. The opening 22 corresponds to the contact pad 12, and the contact pad 12 is exposed from the bottom of the opening 22. An insulating layer 23 is arranged on a sidewall of the opening 22. A rewiring layer 24 is arranged on the insulating layer 23 and at the bottom of the opening 22. The rewiring layer 24 is electrically connected to the contact pad 12. Solder balls 25 are electrically connected to the rewiring layer 24. The electrical connection between the contact pad 12 and other circuits is realized by electrically connecting the solder balls 25 to the other circuits.
The second surface of the wafer 1 is provided with a cutting trench 21 extending towards the first surface, in order to facilitate cutting off the packaged image sensing chip.
Before the solder ball 25 is arranged on the second surface of the wafer 1, solder mask ink 26 is required to be applied on the second surface. Normally the cutting trench 21 and the opening 22 are also filled with the solder mask ink 26 for the purpose of protection and insulation.
However, since the opening 22 is completely filled with the solder mask ink 26, a stress is generated by thermal expansion and contraction of the solder mask ink 26 in the subsequent reflow soldering and reliability testing. The stress is applied to the rewiring layer 24, and the rewiring layer 24 is easily detached from the contact pad 12 under the stress, resulting in a defective chip, which becomes the technical problem desired to be solved by those skilled in the art.